Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Independent Gate Finfet Sram Cell Using Leakage Reduction Techniques

1 Research Scholar of Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India 2 Professor, Dept. of Electronics and Communication, Sagar Institute of Research & Technology, Bhopal, Madhya Pradesh, India. __________________________________________________________________________________________ Abstract: Scaling of devices in bulk CMOS technology contributes to short channel effe...

Finfet Based Sram Design for Low Power Applications

Industry demands Low-Power and HighPerformance devices now-a-days. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thicknes...

Comparison of Conventional 6T SRAM cell and FinFET based 6T SRAM Cell Parameters at 45nm Technology

When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...

the role of task-based techniques on the acquisition of english language structures by the intermediate efl students

this study examines the effetivenss of task-based activities in helping students learn english language structures for a better communication. initially, a michigan test was administered to the two groups of 52 students majoring in english at the allameh ghotb -e- ravandi university to ensure their homogeneity. the students scores on the grammar part of this test were also regarded as their pre...

Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM Cells